1. Technical Field
This disclosure relates to the scan-test of digital integrated circuits, such as integrated circuits having a low pin count.
2. Description of the Related Art
FIG. 1 is intended to illustrate a conventional scan-test principle. A digital integrated circuit may be decomposed in subsets of combinatorial logic functions 10 connected together by flip-flops 12, usually latches, clocked by a common clock CK. Latches 12 are also connected to a common reset line RST.
In order to test the circuit, normal operation of the circuit is interrupted in order to place known values in the latches 12 through a mechanism described hereinafter. Normal operation of the circuit is then resumed for a number of clock cycles CK, after which the circuit is again stopped in order to retrieve the states of the latches through the same mechanism and compare them to expected values.
In order to write test values, or a test vector, in latches 12 of the circuit to test, the circuit is placed in a scan mode by a scan-enable signal SC-EN. In this mode, the latches 12 are connected in a shift register configuration, typically through multiplexers 14. Each latch 12 in this case is preceded by a multiplexer 14 having a first input receiving the signal normally intended for the data input of the latch, provided by a subset of combinatorial logic 10. A second input of the multiplexer, selected by the active state (1) of signal SC-EN, is connected to the output of the preceding latch 12.
Thus, when signal SC-EN is active, the latches are chained in a shift register configuration, clocked by clock CK. The second input of the first multiplexer of the chain forms the scan-in input SC-IN of the shift register, through which the test vector is introduced in series. The test vector has one bit for each latch. The output of the last latch of the chain forms the scan-out output SC-OUT of the shift register, through which is extracted in series the test result set corresponding to the last introduced test vector.
Between the introduction of a test vector and the extraction of a test result set, signal SC-EN may be disabled to let the circuit operate normally during one or several clock cycles with the values of the test vector as initial values in the latches. This operation produces new values in the latches, forming the result set that is extracted when signal SC-EN is again enabled.
It appears that this test technique requires five signals, SC-IN, SC-OUT, SC-EN, CK and RST. These five signals should normally be available on distinct pins of the circuit to test. This happens to be what the JTAG standard (IEEE std 1149.1) specifies, in defining communication protocols according to a similar principle. The clock and reset pins CK, RST, are available on most digital integrated circuits. The signals SC-IN and SC-OUT may correspond with two input/output pins of the circuit, the roles of which may be configured by commands provided on an additional pin dedicated to the test configuration, usually called TMC (Test Mode Configuration). The circuit thus has a minimum of 8 pins, including two power supply pins.
In some digital circuits it is desirable to reduce the pin count, especially of the pins dedicated to the test. U.S. Pat. No. 7,739,566 discloses a solution reducing the pin count to five, including two power supply pins, two input/output pins, and a clock pin. One of the input/output pins is used for receiving both the test commands and the test vectors, and the other input/output pin is used for extracting the test results. The signal determining the scan and capture phases (SC-EN) is generated internally by a state-machine in response to commands received on the input pin.